The manufacturing of various electronic devices (including but not limited to for example, microprocessors, storage devices, graphic processors, analog to digital converters, digital to analog converters, signal processors, image processors, etc.) now requires the cost-effective production of very small structures and features, e.g., structures and features having a characteristic dimension at the micrometer or nanometer size scale. This manufacturing includes the formation of electrically conductive material(s) (e.g., aluminum, copper, etc.) and electrically insulating dielectric material(s) (e.g., silicon dioxide, silicon nitride, etc.) on or as part of a substrate. Moreover, the electrically conductive material(s) are typically separated by regions of dielectric material(s) so as to define electrical elements (e.g., transistors, capacitors, etc.) and interconnections between such electrical elements.
Many electronic devices include multiple layers of electrical elements and/or interconnections (e.g., interconnect layer(s)). Each interconnect layer comprises conductive material(s) separated by dielectric material(s). As an example, a first layer of dielectric material is formed on an electrically conductive material (first conductive layer). A second layer of dielectric material is formed on the first layer of dielectric material. Trenches (e.g. lines) are formed in the second layer of dielectric material, and vias (e.g., holes) are then formed in the first layer of dielectric material. Electrically conductive material is subsequently formed in the trenches and vias so as to electrically connect the now electrically conductive trenches (second conductive layer) to the electrically conductive material (first conductive layer) through the now electrically conductive vias.
Copper is commonly used as the electrically conductive material in electronic devices. Copper can be used to fill trenches and/or vias (or other, similar features) of an electronic device. A description of a method for forming a copper interconnection between electrical elements formed in or on a substrate (e.g. semiconductor) follows. The formation of a copper interconnection etches a structure (e.g., trenches and/or vias) in a dielectric material (e.g., silicon dioxide). A barrier layer (e.g., tantalum and/or tantalum nitride) is formed on the dielectric material. The barrier layer prevents diffusion of copper into the dielectric material. The barrier layer should also adhere well to the dielectric material and to the copper subsequently formed on the barrier layer. A seed layer of copper is formed on the barrier layer. Copper is then formed to fill the trench or via using a bulk formation process (e.g., an electrochemical deposition process).
The formation of copper interconnects includes two copper formation steps and because copper formed using the bulk copper formation process does not nucleate and/or adhere well on the formed barrier layer. This necessitates the formation of a copper seed layer, using a process other than a bulk formation process, on which the bulk copper does nucleate and/or adhere, for example, by providing an electrochemically reactive layer for subsequent electrochemical deposition of copper. Additionally, the two copper formation steps and are used because the copper seed layer formation step by itself (e.g., physical vapor deposition, sputtering) does not adequately fill the vias and trenches because of non-conformal step coverage produced by the physical vapor deposition process (e.g., breadloafing or excessive overhang of deposited material at the top of a trench, via or other feature).
In an alternative process or method for forming a copper interconnection between electrical elements formed in or on a substrate (e.g. semiconductor), the seed layer can be a material (e.g. ruthenium, platinum, etc.) other than copper on which copper formed using the bulk copper formation process does nucleate and/or adhere well (e.g., electrochemical deposition). In another variant, the barrier layer formed can be a material like ruthenium on which copper can be satisfactorily formed (e.g. with good nucleation and/or adhesion) during the bulk formation so as to eliminate the need for the copper seed layer.
Physical vapor deposition (PVD) has been used to form a barrier layer in methods such as those described above with reference to FIGS. 1 and 2. However, as feature sizes shrink, the barrier layer (which has higher resistivity as compared to copper) consumes an increasing percentage of the total interconnect (e.g. via and line) volume for a fixed barrier layer thickness which limits the overall conductivity of the interconnect structure(s). It therefore has become necessary to form or deposit ultra-thin barrier materials (e.g., on the order of less than 50 angstroms thick) to maximize copper volume within the interconnect structure(s). Overhang or breadloafing has increasingly become a problem when using PVD to form an ultra-thin barrier layer. One approach to reduce this problem has been the use of ionized PVD (and can be in conjunction with resputtering) whereby sputtered atoms of the barrier layer material are ionized and made to move more directionally toward the bottom regions of features which reduces overhang. Resputtering enables some localized shaping and/or redistribution of deposited material.
One limitation of ionized PVD is that the achievable step coverage (or conformality of the deposited material with respect to the substrate topography) is lower than desired, e.g., can be less than 20% for 5:1 aspect ratio (height to width), 0.1 μm via structures, especially at the via mid to lower sidewall regions. Also, the trench and via bottom and sidewall surfaces can be roughened as a result of the ionized PVD process; this can produce an increase in electron scattering effects with an undesirable increase in line and via resistance. Additionally, PVD processes are line-of-sight which may not produce process results across an entire substrate that are as uniform as desired because the location of a feature on the substrate and characteristics of the feature (e.g., aspect ratio, orientation) can affect the step coverage achieved for that feature.
Recently, atomic layer deposition (ALD) has been used in barrier layer formation. The use of ALD to form a barrier layer can mitigate problems encountered in the use of PVD. For example, ALD enables uniform, conformal deposition of ultra-thin barrier layers that have become necessary to accommodate the increasingly small features and structures being formed on semiconductor substrates. Relative to PVD, ALD can also provide improved repeatability of process results, as well as more uniform process results across an entire substrate. However, the reactants (e.g., precursor, reactants, and carrier gases, etc.) used in an ALD process are undesirably susceptible to diffusion into the dielectric material (particularly the porous low-k dielectric materials that are increasingly being used). In addition, ALD barrier layers often suffer from poorer adhesion properties (e.g., copper adhesion to ALD TaN is worse than to PVD Ta).
A combination of PVD and ALD has also been used. However, while this can alleviate some of the problems described above, others persist. The most significant ongoing problem is the incompatibility of ALD barrier materials with porous dielectric materials due to the diffusion of the ALD reactants into the pores of porous dielectric materials.
Molecular self-assembly is a technique that can be used to produce very small structures and features, e.g., structures and features having a characteristic dimension at or below the nanometer size scales. Molecular self-assembly can be used to produce a variety of material formations, such as molecular monolayers (often referred to as self-assembled monolayers, or SAMs), molecular multilayers and nanostructures (e.g., nanotubes, Buckey balls, nanowires). For example, a SAM has been used as a barrier layer (replacing the deposited barrier layer, as described above) that inhibits diffusion of copper into a dielectric material. However, this SAM inhibits copper diffusion into SiO2 or fluorinated SiO2, both of which are non-porous dielectric materials.
Porous dielectric materials provide additional challenges to inhibiting diffusion because the pores of porous dielectric materials provide another diffusion pathway for foreign material (e.g., barrier layer material, copper) into the dielectric material. SAMs have been proposed for use as bulk diffusion barrier layers, especially for use with dense dielectric materials such as silicon dioxide. There is a need for the prevention of diffusion of foreign material through the exposed pores of porous dielectrics.
Incorporation By Reference
Each publication, patent, and/or patent application mentioned in this specification is herein incorporated by reference in its entirety to the same extent as if each individual publication and/or patent application was specifically and individually indicated to be incorporated by reference.